| 摘要 |
<p>A computing system having a plurality of processing elements (210) for concurrent execution of a serial program is able to run applications developed for single processors without change to source code or object code by allocating instructions to various processors depending upon the addresses contained within their operand(s). The memory space of the system is partitioned into individual memory blocks which are controlled by dedicated memory coordination units (230) and plural memory coordination units are associated with each processor in a combinatorial connection arrangement (figure 6). This allows instructions to execute on processors which inherently have all the information needed in their registers at the time of execution thus enhancing performance. The plurality of memory coordination units (230) connected to a processing element (210) are associated with FIFO queues (750-770) which are utilized to ensure sequential consistency including the cases of indirect addressing and conditional jumps.</p> |
