发明名称 |
Integrated circuit device structure with dielectric and metal stacked plug in contact hole |
摘要 |
A method is provided for patterning a submicron semiconductor layer of an integrated circuit, and an integrated circuit formed according to the same. A conductive structure is formed on the integrated circuit. A dielectric layer is formed over the integrated circuit. A contact opening is formed in the dielectric layer exposing a portion of the underlying first conductive structure. A barrier layer is formed on the dielectric layer and in the contact opening. A substantially conformal layer is formed over the barrier layer and in the contact opening. The conformal layer is partially etched away wherein the conformal layer remains only in a bottom portion of the contact opening. A second conductive layer is formed over the barrier layer and the remaining conformal layer.
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申请公布号 |
US5523624(A) |
申请公布日期 |
1996.06.04 |
申请号 |
US19930112863 |
申请日期 |
1993.08.26 |
申请人 |
SGS-THOMSON MICROELECTRONICS, INC. |
发明人 |
CHEN, FUSEN E.;MILLER, ROBERT O.;DIXIT, GIRISH A. |
分类号 |
H01L21/28;H01L21/285;H01L21/302;H01L21/3065;H01L21/768;(IPC1-7):H01L29/417;H01L29/43 |
主分类号 |
H01L21/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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