BRIDGE BETWEEN BUSES IN A SYSTEM HAVING A PLURALITY OF BUSES WITH DIFFERENT MEMORY ADDRESSING CAPACITIES AND HAVING AN ARRANGEMENT FOR REALLOCATING MEMORY SEGMENTS WITHIN THE SYSTEM MEMORY MAP

摘要

A computer system that has two buses with different memory addressing capacitiesand a first bus master that generates M-bit addresses is provided with a bridge between the two buses. In order to generate N-bit addresses for use on the second bus, a direct memory access (DMA) controller on the bridge produces P bits, where P + M = N. The P bits are concentrated with the M bits to form an N-bit address used on the second bus to address memory. The addition of P bits reallocates the memory segment addressable by the M-bits to any location within the memory map addressable by an N-bit address.