| 摘要 |
PURPOSE: To obtain a high speed low power consumption semiconductor memory by reducing the sub-threshold current at the time of stand-by of a gate circuit and lowering the voltage difference between a main and sub power supply voltage transmission lines. CONSTITUTION: A main power supply voltage transmission line 100 for transmitting a power supply voltage VCH and a sub-power supply voltage transmission line 110 are provided, as one power supply, for a gate circuit G. A high resistance element R is connected between main and sub-power supply voltage transmission lines 100, 110 and a capacitor C comprising an insulated gate FET is connected with the sub-power supply voltage transmission lines 110. The fate circuit G is operated with a voltage VC on the sub-power supply voltage transmission lines 110. Consequently, the voltage on the sub-power supply voltage transmission lines 110 is sustained at a level being balanced with the sub- threshold current of the gate circuit G and the voltage VC is sustained stably by means of the capacitor C. |
