| 摘要 |
A serial bus host controller arbiter which organizes data transfer events into three categories, periodic data transfers, which are usually isochronous transfers; aperiodic transfers, which usually are asynchronous transfers; and control transfers. The arbiter fundamentally operates on a periodic basis. At the beginning of each period, the arbiter preferably alternates between periodic transfers and control transfers. When all of the periodic transfers have been completed, the arbiter then provides access to the various asynchronous transfers which are scheduled to occur, alternating with any remaining control transfers. The arbiter gives preference to the periodic events, and if any time within the period is available, which is referred to as the free time, control events are interleaved with periodic events until no free time remains or all are completed. Any remaining time in the period is used cycling through the aperiodic transfers. The arbiter of the preferred embodiment keeps a running total of free time during each period to determine if additional control or aperiodic transfers can occur.
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