| 摘要 |
A data processing system (100) is provided which includes a memory (104), an array (204) of memory cells arranged in rows and columns, each row being addressable by an address. Address generation circuitry (201/202) is provided for generating ones of the addresses for accessing selected ones of the rows in the array (204). An associated memory (203) is coupled to the address generation circuitry (201/202) for translating a first address, received from the address generation circuitry (201/202) and addressing a defective one of the rows of the array (204), into a second address addressing an operative one of the rows in array (204), the second address being sent to the memory.
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