Semiconductor memory device having circuit for activating predetermined rows of memory cells upon detection of disturb refresh test

摘要

When a disturb refresh mode is detected by a mode detecting circuit, a row decoder control circuit simultaneously activates every several word lines of a memory cell array of a block selected by an operation block selecting circuit through a row decoder and a driving circuit, reads out data written in a normal mode, and determines a memory cell having a threshold value lower than that of a design value upon determination of match of read data and written data.