发明名称 |
Adapter for the connection to a clear-channel telecommunication network |
摘要 |
An adapter having a line interface circuit for providing an analog attachment to a network (100). The line interface circuit is provided with a reset input for beginning a resynchronization of the timing of the adapter. The adapter further includes a Digital Phase-locked Loop device DPLL (203) driven by a master clock (306) which provides the timing and synchronization signals to the line interface circuits (201). The DPLL (203) divides a master clock down to an internal INT clock (309), a phase comparator (303) compares the INT clock with a reference signal (302) which is synchronized with the receive clock (202) extracted from the line by line interface (201). The phase comparison process operates with a Correction Signal (CS) which has a window centered around the falling edge of the INT clock. A frequency correction is initiated when the reference clock falls outside of the correction window and is achieved by inserting or suppressing a master clock pulse at this time. The adapter further includes means for resetting the line interface circuits and the DPLL at the power-on of the adapter, such that the frequency correction apparatus of the adapter causes two adapters attached at separate ends of a transmission medium to evolve toward stable timing states with respect to each other.
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申请公布号 |
US5519737(A) |
申请公布日期 |
1996.05.21 |
申请号 |
US19930048598 |
申请日期 |
1993.04.19 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BRUN, ALAIN;CAZAENTRE, JEAN-MARC;GIULIANO, HENRI;SICSIC, PATRICK |
分类号 |
H04L7/00;H04J3/06;H04L7/033;H04L7/10;H04M3/00;(IPC1-7):H03D3/24 |
主分类号 |
H04L7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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