发明名称 VARIABLE DELAY CIRCUIT
摘要 <p>PURPOSE: To relieve a defective product by speedily adjusting delay time after the completion of a wafer by adjusting the delay time by switching a control signal to be supplied from a permanent memory means and changing the number of stages of an inverter for delay. CONSTITUTION: A control signalϕC is switched by cutting off a fuse inside a permanent memory means 6 by irradiating it with a laser. When the control signalϕC from the means 6 is 'L', a switch means 2 is turned on, delay elements 1 and 3 are serially connected, an input signalϕin is delayed by the elements 1 and 3, and the long delay time is provided from an AND gate 5. On the other hand, when the control signalϕC is 'H', the switch means 2 is turned off, the elements 1 and 3 are disconnected and a switch means 4 is turned on, so that the input to the element 3 can be fixed at a power supply potential VCC and the output of the element 3 can become 'H'. Therefore, since the input signalϕin is delayed by only the element 1 and outputted from the AND gate 5, the short delay time is provided. Thus, the yield of an integrated circuit is improved by speedily adjusting the delay time after the completion of the wafer.</p>
申请公布号 JPH08130448(A) 申请公布日期 1996.05.21
申请号 JP19940267605 申请日期 1994.10.31
申请人 SANYO ELECTRIC CO LTD 发明人 MOGI HIROSHI;IIJIMA SATOAKI
分类号 G11C11/407;G11C11/401;G11C11/4076;H03K5/13;H03K19/173;(IPC1-7):H03K5/13 主分类号 G11C11/407
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