Semiconductor memory device with external capacitor to charge pump in an EEPROM circuit

摘要

A semiconductor memory device having a memory cell array with a plurality of transistors (memory cells MC) disposed in a matrix form capable of electrically altering data. In writing data to a plurality of memory cells (MC), a write voltage (Vpp') is applied to the plurality of memory cells (MC) from a plurality of write circuits (7). The write voltage is generated by boosting an internal voltage (VCC) by a charge pump circuit (21). In writing data, one of the following methods is used. The plurality of write circuits (7) are sequentially activated by a write control circuit (20) at intervals of delayed timings. The operating point of each memory cell (transistor)(MC) is controlled by operating point control means so as to reduce a current. A capacitor is connected to the output side of the charge pump circuit, and a boosted write voltage is supplied via the capacitor to the write circuit.