首页
产品
黄页
商标
征信
会员服务
注册
登录
全部
|
企业名
|
法人/股东/高管
|
品牌/产品
|
地址
|
经营范围
发明名称
Menetelmä materiaalien liittämiseksi yhteen diffuusiomenetelmällä käyttäen hopea/germanium-lejeerinkejä ja hopea/germanium-lejeerinki käytettäväksi tässä menetelmässä
摘要
申请公布号
FI962115(A)
申请公布日期
1996.05.17
申请号
FI19960002115
申请日期
1996.05.17
申请人
JOHNS, PETER GAMON
发明人
JOHNS, PETER GAMON
分类号
B23K35/30;B23K20/233;C22C5/08;(IPC1-7):B23K;C22C
主分类号
B23K35/30
代理机构
代理人
主权项
地址
您可能感兴趣的专利
LOW TEMPERATURE POLY-SILICON THIN FILM TRANSISTOR AND FABRICATION METHOD THEREOF, ARRAY SUBSTRATE AND DISPLAY DEVICE
CONTACT STRUCTURE OF SEMICONDUCTOR DEVICE
INSULATED GATE BIPOLAR TRANSISTOR
LDD-FREE SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD OF THE SAME
METHOD OF FORMATION OF GERMANIUM NANOWIRES ON BULK SUBSTRATES
LOW TEMPERATURE FABRICATION OF LATERAL THIN FILM VARISTOR
PIXEL UNIT, ARRAY SUBSTRATE, DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME
ORGANIC LIGHT EMITTING DIODE DEVICE AND METHOD FOR FABRICATING THE SAME
FLEXIBLE SCREEN AND BEND IDENTIFYING METHOD THEREOF, FLEXIBLE DISPLAY APPARATUS
LIGHT DETECTION DEVICE
SOLAR BLIND ULTRA VIOLET (UV) DETECTOR AND FABRICATION METHODS OF THE SAME
SENSOR FOR DUAL-APERTURE CAMERA
MANUFACTURE METHOD OF LTPS AND MANUFACTURE METHOD OF TFT SUBSTRATE
METHODS OF FORMING MEMORY DEVICES WITH ISOLATION STRUCTURES
METHODS AND APPARATUSES INCLUDING AN ACTIVE AREA OF A TAP INTERSECTED BY A BOUNDARY OF A WELL
APPARATUS AND METHOD FOR BONDING CHIPS
Interconnect Structures, Packaged Semiconductor Devices, and Methods of Packaging Semiconductor Devices
Combined wafer production method with laser treatment and temperature-induced stresses
METALLIZATION OF THE WAFER EDGE FOR OPTIMIZED ELECTROPLATING PERFORMANCE ON RESISTIVE SUBSTRATES
TAPE FOR ELECTRONIC DEVICES WITH REINFORCED LEAD CRACK
