| 摘要 |
PURPOSE: To provide a PLL circuit with short lock-in time and with a power saving effect by holding control voltage controlling a voltage control oscillator. CONSTITUTION: Control voltage generated in a charge pump 20 and a loop filter 30 is held by a first capacitor 32 in accordance with a result obtained by comparing the oscillation frequency of the voltage control oscillator 40 and a reference frequency by a phase frequency comparator 10, and it is fed back to the voltage control oscillator 40. While the PLL circuit is operated, a second capacitor 80 is charged by the voltage through a switch 51, a differential amplifier 61, a P-channel transistor 71 and a switch 52. While the PLL circuit not operated, the first capacitor 32 is charged by the voltage of the second capacitor 80 through the switch 51, the differential amplifier 61, the P-channel transistor 71 and the switch 52. |
