发明名称 Content addressable memory circuitry and method of operation
摘要 Content addressable memory circuitry and a method of operation are provided. First information is stored. A logic state of a first match line is selectively modified in response to a comparison between the first information and second information. Also, third information is stored. A logic state of a second match line is selectively modified in response to a comparison between the third information and fourth information. A logic state of the second match line is selectively modified in response to the logic state of the first match line.
申请公布号 US5517441(A) 申请公布日期 1996.05.14
申请号 US19940355864 申请日期 1994.12.14
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 DIETZ, CARL D.;HOOVER, KATHRYN J.
分类号 G11C15/00;G11C15/04;(IPC1-7):G11C15/00 主分类号 G11C15/00
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