Schaltungsanordnung zur Übertragung von Taktsignalen und Taktsignalenempfanganordnung

摘要

A clock information transmitting device coupled to a digital processing circuit which receives a transmission signal and generates a coded transmission signal includes a PLL circuit (17) for generating a first signal and a sampling clock signal, both being synchronized with a synchronizing signal in the transmission signal. The sampling clock signal is used in the digital processing circuit. A clock information generating part (6, 7, 13, 14, 15-1 - 15-10, 16) counts pulses of a transmission clock signal and generates clock information indicating a number of pulses of a transmission clock signal in response to one of the synchronizing signal and the first signal generated by the PLL circuit. A multiplexer (18) outputs a multiplexed signal including the clock information and the coded transmission signal to a transmission path.