A clock extraction circuit for retiming a ternary data stream derives first and second binary streams DP, DN corresponding respectively to the positive and negative going positions of the ternary data stream, These binary streams are combined 31 to provide a further binary stream which is retimed to a local clock SLCLK whereby to generate 32 a reference stream for retiming (23, Fig. 2) the first and second binary data streams to said reference stream. The retimed binary data streams are combined (24) to generate a retimed ternary data stream. <IMAGE>
