发明名称 INPUT LEVEL TEST CIRCUIT
摘要 PURPOSE: To enable a test to be performed without receiving the effect of noise due to the operation of an internal circuit by inputting a control signal controlling a test mode and a usual operation mode to both of an input buffer circuit and an output buffer circuit. CONSTITUTION: In a usual operation mode, a control signal input terminal 100 is set high and all of the transistors 1, 4 of input buffer circuits 200, 201 and the transistors 6, 11 of output buffer circuits 202, 203 are set to a non-continuity state. The output signal of an internal circuit 19 is outputted to pads 16, 17 through the output buffer circuits 202, 203. Next, at the time of a test mode, the input terminal 100 is set low and all of the transistors 6, 11 of the output buffer circuits 202, 203 and the transistors 1, 4 of the input buffer circuits 200, 201 are set to a continuity state. That is, the logical signals corresponding to the signal levels of the input buffer circuits 200, 201 are outputted to the output buffer circuits 202, 203 and the test of an input level can be performed without relying on the output of the internal circuit 19.
申请公布号 JPH08114653(A) 申请公布日期 1996.05.07
申请号 JP19940274227 申请日期 1994.10.14
申请人 NEC CORP 发明人 MASUKO HIDEKATSU
分类号 G01R31/28;G06F11/22;H01L21/66;H01L21/822;H01L27/04 主分类号 G01R31/28
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