发明名称 |
Synchronous data row generating circuit |
摘要 |
A rate generating portion generates a second rate signal comprising a desired first rate signal having arbitrary time intervals preceded by a preceding rate signal composed of (N+1) pulses, a data row generating portion composed of N logic circuits and N D-type flip-flops generates an arbitrary data row with the second rate signal as a synchronizing clock, a preceding rate masking circuit masks the preceding rate signal in the second rate signal to output the first rate signal and a D-type flip-flop receives the output of the data row generating portion at the data input terminal thereof and the output of the preceding rate masking circuit at the clock input terminal thereof to generate a data row in synchronism with the first rate signal. As a result, it is possible to provide a synchronous data row generating circuit which operates stably without using the conventional delay elements for adjustment since the data row generating portion therein is composed of synchronous circuits.
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申请公布号 |
US5514991(A) |
申请公布日期 |
1996.05.07 |
申请号 |
US19950426466 |
申请日期 |
1995.04.19 |
申请人 |
ANDO ELECTRIC CO., LTD. |
发明人 |
UEHARA, TAKAFUMI;FUJII, HARUHIKO |
分类号 |
G01R31/3183;G01R31/3181;H03K3/64;(IPC1-7):H03L7/00;H03K3/017 |
主分类号 |
G01R31/3183 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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