发明名称 Circuit structure and method for stress testing of bit lines
摘要 <p>A plurality of bit lines is arranged in columns and grouped into a first set of bit lines and a second set of bit lines. Each bit line in the first set of bit lines alternates with each bit line in the second set of bit lines. First switching means electrically connects the first set of bit lines to a first voltage level and, simultaneously, second switching means connects the second set of bit lines to a second voltage level. This permits a bit line stress test that will reveal defects or failures in a memory chip. &lt;IMAGE&gt;</p>
申请公布号 EP0709853(A1) 申请公布日期 1996.05.01
申请号 EP19950307657 申请日期 1995.10.27
申请人 STMICROELECTRONICS, INC. 发明人 MCCLURE, DAVID C.
分类号 G11C11/401;G11C29/00;G11C29/06;G11C29/34;G11C29/50;(IPC1-7):G11C29/00 主分类号 G11C11/401
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