| 摘要 |
<p>Redundant mapping tables (204', 206') for use in processors (100) that rename registers (302, 306) and perform branch prediction is presented. The redundant mapping tables (204', 206') include a plurality of redundant RAM cells (600). In the event of a branch instruction, the redundant RAM cells (600) can save the contents of the primary RAM cells (500) in a single clock cycle before the processor decodes and executes subsequent instructions along a predicted branch path. Should the branch instruction be mispredicted, the redundant cells (600) can restore the primary RAM cells (500) in a single clock cycle. A plurality of levels of redundant RAM cells (600) may be used to enable the nesting of a plurality of branch predictions at any one time.</p> |
