Store processing method in a pipelined cache memory

摘要

A cache memory apparatus and microprocessor therewith has a first address register for a tag memory and a second address register for a data memory, a tag entry decoder and a data entry decoder. Lower order bits of the contents stored in the first address register are transferred to the second address register through a transferring path in a write operation. Tag comparison and a data write of a result of the preceding comparison are executed in parallel in the same clock period, and thereby speed of processing is higher in the case of consecutive write operations at a write hit.