| 摘要 |
PURPOSE: To provide a frame synchronizing circuit which can decrease the number of wirings and pins, can evade the wrong acquisition of synchronism and can increase the margin of an equal-length wiring by providing a frame synchronization deciding period setting means to properly set a synchronization detection period. CONSTITUTION: At a data input part 100, the data Data-in sent from a device of the transmission side are fetched according to a bit clock BLCK-in. Then the parallel data Sync-Pat equal to (n) bits, i.e., the frame synchronization pattern length are shifted by one bit and outputted out of the data Data-in. At the same time, the data Data-in are outputted in sequence by an amount equal to N bits as the data Data-Main. The part 100 consists of flip-flop circuits 101 which are continuously connected together and secures the coincidence between (n) bits received at a frame synchronizing signal detection part 200 and the frame synchronization pattern length that is previously decided. Then an enable signal is produced at a frame synchronization deciding part 300. |
