Verbesserte Vorrichtung zum Reduzieren von Verzögerungen aufgrund von Verzweigungen

摘要

To reduce the delays produced by branch instructions a computer architecture utilizes a branch processor 100 having a branch memory 102 for storing information specifying a plurality of branch instructions that are contained in a code sequence. The branch memory stores information specifying the target address of each branch instruction and the location of the branch instruction with respect to the beginning of the code sequence. The branch processor receives the results of the various comparisons that determine if the conditions associated with the various branches are satisfied, and preferably stores, 112, the identity of the branch that is closest to the begining of the code sequence for which the condition associated therewith has been satisfied. This branch will be referred to as the highest branch enabled. The actual branching operation is carried out in response to the receipt of an execute branch instruction which specifies one or more of the branches stored in the branch memory. If one of the branches specified in the execute branch instruction matches the highest branch enabled, then the code sequence continues at the target address of the highest branch enabled. Cache lines associated with the target address may be prefetched, 140. <IMAGE>