发明名称 Coprocessor executing pipeline control for executing protocols and instructions
摘要 The interface portion of a coprocessor is provided with a FIFO (First-In First-Out) buffer and means for accepting instructions in succession. Pipeline control of the instructions becomes possible in this way, and protocol means associated with a microprocessor is also provided.
申请公布号 US5504912(A) 申请公布日期 1996.04.02
申请号 US19920830460 申请日期 1992.02.05
申请人 HITACHI, LTD.;HITACHI ENGINEERING CO., LTD. 发明人 MORINAGA, SHIGEKI;NAKAGAWA, NORIO;WATABE, MITSURU;OHBA, MAMORU;KIDA, HIROYUKI;KAZIWARA, HISASHI;ASAI, TAKESHI;TATEZAKI, JUNICHI
分类号 G06F7/00;G06F9/38;G06F15/16;G06F15/167;(IPC1-7):G06F15/16 主分类号 G06F7/00
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