Pulse stuffing synchronization control system

摘要

A pulse stuffing synchronization control system includes a memory circuit for storing a plurality of items of lower digital hierarchy data input thereto in parallel, a clock generator for generating a writing clock signal and a control clock signal, a data writing controller for writing the plurality of items of the lower digital hierarchy data in synchronism with the writing clock signal, a read clock output circuit for generating a reading clock signal, a pulse stuffing controller for generating stuffing information based on the difference between the phases of a transmission clock signal and the control clock signal generated by the clock generator and for controlling the number of pulses of the writing clock signal based on the stuffing information, and a data read controller for reading out the plurality of items of the lower digital hierarchy data from the memory means in synchronism with the reading clock signal processed by the pulse stuffing controller, so that higher digital hierarchy data is output from said memory means in synchronism with the reading clock signal processed by the pulse stuffing controller.