| 摘要 |
PURPOSE: To reduce an erasing section from a design at the storage node of the capacitive element of a memory cell, and to obtain a desired capacitance value by forming the storage node of the capacitive element of the memory cell to the upper layer of a bit line and arranging the long side section of the storage node in parallel with a word line. CONSTITUTION: Third conductive layers for forming storage nodes 110 are formed onto the whole surface on an interlayer insulating film 116 on bit lines 108. The third conductive layers are connected electrically to other source-drain regions of the transistor element of a memory cell by storage node contacts. Long sides are disposed in parallel with word lines 107 and short sides in parallel with the bit lines 108 among the two adjacent word lines 107 while the third conductive layers are crossed and arranged on the bit lines 108, to which corresponding memory cells are connected. Accordingly, the opposed areas of the storage nodes and a cell plate are increased, thus reducing appearance sections from a design at the storage nodes. |
