| 摘要 |
<p>PURPOSE: To eliminate the influence on the processing performance of an MPU even if the amount of communication information increases and to suppress the increase in circuit scale by providing an OR means and placing the MPU in wait operation when the output of the logic means is at a specific level. CONSTITUTION: When a hardware circuit is in write operation and the MPU is in read operation, a main clock from another asynchronous circuit 1 and data are inputted to a clock generation part 22 and a data transfer part 21 in the hardware circuit. The clock generation part 22 uses the main clock to generate a clock for transfer and a write clock having width corresponding to one main clock, and sends the former to the data transfer part 21 and the latter to a logic part 24. A data transmission part 21, on the other hand, writes the inputted data in a register 23 by using the rise of the clock for transfer. Then the logic part 24 ORs the write clock with an address decoding pulse to generate and applies a wait control signal XBUSY for delaying the read/write timing of the MPU 3 by a specific time to the READY terminal of the MPU.</p> |
