| 摘要 |
<p>PURPOSE: To shorten the required for batch erase processing by providing a means which consecutively impresses erase signal without checking the erase state of memory cell before reaching the impressing time of the erase signal required for the previous batch erase. CONSTITUTION: A control means 2 issues an initialization signal 13 to zero the erase pulse impressing time count 5 and set the selection signal 19 at the effective level, issuing the erase control signal for a unit of time. A control signal generating means 3 outputs the erase signal 22 to an EEPROM 1 for a unit of time to add one to the counting means 5 and to output to a bus 25. A comparison means 6 compares the number of impression times of the erase pulses on the bus 25 with that at the previous batch erase on a bus 27 to issue a coincidence signal 14. The control means 2 sends a batch erase head address to the bus 15 to issue a read signal 16 when the signal 14 is active. The EEPROM 1 outputs the memory data of the memory cell corresponding to the internal address 15 to a bus 12, and the control means 2 judges whether the cell is already erased or not. Succedingly the memory cells are batch-erased through the judgment of the final address and the confirmation of the output of the coincidence signal. When unerased yet, the number of impression times of erasing pulses and that of selection reference are compared. when the former is greater than the latter, the EEPROM 1 is judged to be defective. Otherwise, erase pulses are impressed for a unit of time.</p> |
