| 摘要 |
<p>PURPOSE: To obtain a CMOS buffer circuit in which the operating speed is not lowered while simultaneously decreasing a switching noise when power supply voltage drops. CONSTITUTION: A first gate circuit 11 is provided with an NMOS transistor QN13 for clamp on the side of the source of an NMOS transistor QN12. This transistor QN13 is connected to an NMOS transistor QN14 for switch in parallel. A second gate circuit 12 is provided with a PMOS transistor QP23 for clamp on the side of the source of a PMOS transistor QP22. This transistor QP23 is connected to a PMOS transistor QP24 for switch in parallel. The PMOS transistor QP31 and the NMOS transistor QN31 composing an output circuit are driven by the outputs of first and second gate circuits 11 and 12, respectively. A switch control circuit 13 detects that power supply voltage becomes a prescribed level or below and performs on-drive for an NMOS transistor QN14 for switch and a PMOS transistor QP24.</p> |
