| 摘要 |
PURPOSE: To shorten a plating wiring process, improve heat dissipation efficiency of semiconductor by PHS, and enhance mechanical strength of semiconductor, by forming plating electrodes and plating wiring on the substrate surface, and forming a metal film on the inner surfaces of viaholes and the back of the substrate. CONSTITUTION: Source electrodes 102, drain electrodes 103 and gate electrodes 104 of FET's formed on the surface of a GaAs substrate 101, and dry-etching type viaholes 105 which penetrate the GaAs substrate from the surface to the back and are adjacent to the source electrodes 102 are formed. Power supplying layers 106 for plating the viahole part which cover the surface aperture part and are connected with the source electrodes 102 are formed. Plating electrodes 107 which are stacked on the layers 106 so as to cover them and are connected with the source electrodes 102 via the power supplying layer 106 are formed. PHS is formed on the back and in the viaholes 105 by an electrolytic plating method, and come into contact with the power supplying layer 106, in the viahole 105 surface aperture part. |
