| 摘要 |
<p>PURPOSE: To reduce the power consumption without lowering the operation speed of a microcomputer in a microcomputer application system of cache memory system. CONSTITUTION: When the write cycle signal of CPU 1a is detected by a write pulse detecting part 10, a counter 11 is cleared, a comparator 13 compares the counting of the counter 11 with the counting of a control register 12 and an idle state signal is outputted from a state detecting signal outputting part 14 at the time of coincidence. The idel state of the CPU 1a is detected by a clock selector 18, change-over is executed from a standard clock 16 into the clock 17 being about a half of the standard one and it is supplied to a pheripheral circuit 9. When a mishit detecting part 15 detects the mishit of the CPU 1a, an idle state releasing signal is outputted to the state detecting signal outputting part 14, the idle state signal is stopped, the clock is changed- over from the clock 17 into the standard clock 16 and it is supplied to the peripheral circuit 9.</p> |
