发明名称 |
Memory cache with interlaced data and method of operation |
摘要 |
A memory cache (14) has a plurality of cache lines (50) for storing a series of contiguous memory elements. Each series of memory elements are interlaced within the corresponding cache line on a element-by-element basis and on a bit-by-bit basis. This storage strategy allows the memory cache to output a subset memory elements within a cache line quickly and in the original contiguous order. The invention may be advantageously incorporated in an instruction cache of superscalar data processor to provide a series of sequential instructions for execution.
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申请公布号 |
US5499204(A) |
申请公布日期 |
1996.03.12 |
申请号 |
US19940270628 |
申请日期 |
1994.07.05 |
申请人 |
MOTOROLA, INC. |
发明人 |
BARRERA, DAVID;LEVITAN, DAVE;RASTEGAR, BAHADOR;ROSSBACH, PAUL C. |
分类号 |
G06F12/08;(IPC1-7):G11C15/00 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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