发明名称 Process of fabricating semiconductor device having flattening stage for inter-level insulating layer without deterioration of device characteristics
摘要 An upper portion of a silicon nitride layer deposited over a silicon oxide layer which in turn covers metal wirings is partially polished for forming a flat surface remaining silicon nitride layer prevents the metal wirings from a strong, corrosive cleaning solution during a cleaning stage of residual oxide particles and contaminant, and the remaining silicon nitride layer and a part of the silicon oxide layer are uniformly etched by dry etchant so as to decrease a parasitic capacitance coupled to the metal wirings.
申请公布号 US5498574(A) 申请公布日期 1996.03.12
申请号 US19950427216 申请日期 1995.04.24
申请人 NEC CORPORATION 发明人 SASAKI, SHUUZOU
分类号 H01L21/302;H01L21/304;H01L21/3065;H01L21/3105;H01L21/3205;H01L21/768;H01L23/522;(IPC1-7):H01L21/302 主分类号 H01L21/302
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