| 摘要 |
PURPOSE: To designate a data processing operation requested by a user in the least number of instructions by multiplying a 1st operand by a 2nd operand by a multiplication accumulation instruction and then adding a 3rd operand to designate the calculation of these arithmetic results. CONSTITUTION: A processor core 102 includes a register bank 106, a multiplication accumulator 118 and a write data register 114 and builds in the N-bit data paths (32-bit data paths) among various function units. In an operation mode, the instruction of an instruction pipeline 116 is decoded by an instruction decoder 118 to produce various core control signals which are sent to the different function elements contained in the core 102. In response to these core control signals, the different parts of the core 102 carry out the 32-bit processing operations, i.e., the 32-bit multiplication, the 32-bit addition, the multiplication accumulation operation with different accuracy, etc. |
