发明名称 METHOD AND STRUCTURE FOR ARRANGING SEMICONDUCTOR DEVICE INTER-CONNECTION FOR REDUCTION OF INITIAL FAILURE CAUSED BY ELECTROMIGRATION DUE TO LOCALLY HIGH CURREHT DENSITY
摘要 <p>PROBLEM TO BE SOLVED: To provide an interconnect layout structure, and its manufacturing method, to reduce failure caused by electromigration in a region, where current density is locally high. SOLUTION: In a first technique, an interconnect structure 10 reduces peak localized interconnect current density by distributing a current flow around the periphery 22 of an interlevel connector 14 in a semiconductor device. In the second technique, the interconnect level is formed of a polycrystalline material, and by only using intrinsically plural branch lines, the two points in the semiconductor device are connected together. Each of branch lines has a line width narrower than that of the central particle size of the polycrystalline material. In a third technique, an interconnect line comprises, intrinsically, plural upper side and lower side straps connected by plural interlevel connectors. Thus a chain structure, wherein substantially the full length between two points in the semiconductor device is connected, is provided.</p>
申请公布号 JPH0864771(A) 申请公布日期 1996.03.08
申请号 JP19950206772 申请日期 1995.07.21
申请人 MOTOROLA INC 发明人 CHIYAARUSU JIEI BAAKAA;MAIKERU ERU DOREIYAA;TOOMASU II JIIKURU
分类号 H01L21/822;H01L23/528;H01L27/04;(IPC1-7):H01L27/04 主分类号 H01L21/822
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