Vector data bypass mechanism for vector computer

摘要

A bypass mechanism in a vector computer is disclosed. The vector register bypasses data to be written in the inner registers (316) from input or output of the write data register (315). The bypass mechanism is mainly realized by a selector (318) and a decoder (317). The selector (318) selects any one of data (3091) to be written in the registers (316) at the timing before 2 cycles, data (3151) to be written in the registers (316) at the timing before 1 cycle, and the read data (3161) from the registers (316). The decoder (317) controls the selector (318) according to a mask signal from the mask register; a signal (3131) of a timing, which is before one cycle, of the mask signal and a bypass signal (3111) from said controller (311). $$