| 摘要 |
PURPOSE:To attain the efficient and unified control of a memory address and thinning position information at the time of thinning access by being equipped with a means to generative virtual address data and a means to allot sample position information at the time of thinning. CONSTITUTION:CPU gives the address assuming a memory space under the thinned condition as data access information and information concerning the thinning position, by allotting a bit. A real address generating part 2 converts them from a reduction rate and the thinning position information to the address to which respective memories M1-M8 of a memory 11 are actually given. When the reduction rate is 1/2, for example, when the access information is 0, 0 is given to memories M1, 3, 5 and 7 as the address, and 1 is given to memories M2, 4, 6 and 8. At such a time, the data read from the memories M1-M8 are 11, 21, 13, 23, 15, 25, 17 and 27. When data rearrangement is executed to these, the data trains of 11, 13, 15, 17, 21, 23, 25 and 27 are obtained, and the thinning of 1/2 is attained. In such a thinning, the thinning position can be changed by the position information in the access information. |
