STRUCTURE OF FUZZY LOGIC CONTROLLER WITH PARALLEL PROCESSING EXPANSIBILITY

摘要

an IF module having a first alpha input register which receives an adequate degree value of a previous module and outputs the received value to a minimum operating unit and a second alpha output register which stores an output value of the minimum operating unit and outputs the stored value to a next module; and a THEN module having a third alpha input register which receives an adequate degree value of a previous module and outputs the received value to a minimum operating unit, whereby the IF and THEN modules are connected by a cascade to perform input/output extension and control rule extension.