发明名称
摘要 PURPOSE:To synchronize a video image due to a projector by allowing each sub equipment to receive a same clock signal of a low frequency from a main device and comparing the phases of clock signals and multiplying them. CONSTITUTION:A phase locked loop circuit 41 (42-4N) and a multiplier circuit 81 (82-8N) in pairs receive clock signals 9 of a low frequency from a main device 1 respectively and compare the phases and multiply them to output a device clock signal 5 of a high frequency respectively. In this case, the main device 1 sends the clock signal 9 of a low frequency such as 1MHz offering easy and simple communication. Thus, sub devices 31,32,...3N, that is, devices 71,72,...7N such as projectors are completely synchronized.
申请公布号 JPH0817489(B2) 申请公布日期 1996.02.21
申请号 JP19900263302 申请日期 1990.10.01
申请人 发明人
分类号 H04N5/04;G05B11/18;H04N5/073;H04N7/18 主分类号 H04N5/04
代理机构 代理人
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