发明名称 Digital phase difference measurement circuit
摘要 The measuring circuit includes a first shift register (1) which receives a reference signal (R) at its input and is clocks by the clock input signal (T). A digital differentiator (2) is coupled to the output of the shift register (1) and to the clock input (T). The output of the differentiator (2) causes a register (4) to store the outputs of a binary counter (3) which counts the clock input pulses (T). A second shift register (5) receives the reference input (R) clocked by the inverted clock signal. A D flip-flop (7) stores the output of the second shift register (5) clocked by the output of an analog differentiator (6) which is coupled to the digital differentiator (2). The output of the D flip-flop is the least significant bit (LSB) of the output binary word (B). The most significant bits (MSBs) of the output binary word are obtained from the register (4).
申请公布号 DE19506007(C1) 申请公布日期 1996.02.22
申请号 DE1995106007 申请日期 1995.02.17
申请人 SIEMENS AG, 80333 MUENCHEN, DE 发明人 KRAMER, RONALF, DIPL.-ING., 81247 MUENCHEN, DE
分类号 G01R25/00;G01R25/08;G01R31/3185;(IPC1-7):G01R25/00 主分类号 G01R25/00
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