| 摘要 |
<p>PURPOSE:To reduce a data transfer quantity and a transfer time by comparing image data having gradation latched by a parallel shift register and held in a parallel latch circuit with comparison data latched by the parallel shift register to control the drive of a recording element. CONSTITUTION:Image data P.DATA in 8-bit or the like having gradation are held by parallel latch circuits L1-L64 via parallel shift registers SR1-SR64 in a driver IC. The data are compared with comparison data C.DATA transferred sequentially depending on a clock period from parallel shift registers CD1-CD64 by comparator circuits C1-C64 and a recording element is driven depending on the result of comparison. Through the constitution that the gradation image data are directly transferred to the driver IC, the data transfer quantity is reduced considerably, the transfer time is reduced and the circuit configuration is simplified. Furthermore, the power application start time for each recording element is deviated and power consumption is reduced by transferring the comparison data sequentially synchronously with the clock.</p> |
