发明名称 |
ROBUST DELAY FAULT BUILT-IN SELF-TESTING METHOD AND APPARATUS. |
摘要 |
This invention relates to a method and apparatus for robust delay fault testing of integrated circuits (IC) with built-in self-testing. For the method, hazardous nodes of the IC are determined. Thereafter, the topology of the IC can be modified to include a cut-point at hazardous nodes of the circuit. Input of the IC to the cut-point is diverted to an observation point. An out-put multi-input signature register (MISR) at the observation point generates a first signature. An output MISR provides a second signature for outputs to the IC. During testing, a hazard-free input pattern is applied to the IC and the generated first and second signatures are compared to known correct signatures. |
申请公布号 |
EP0663092(A4) |
申请公布日期 |
1996.02.14 |
申请号 |
EP19940922668 |
申请日期 |
1994.07.21 |
申请人 |
RUTGERS UNIVERSITY |
发明人 |
BUSHNELL, MICHAEL, L.;SHAIK, IMTIAZ, COOK CAMPUS |
分类号 |
G01R31/28;G01R31/30;G06F11/267;(IPC1-7):G06F17/50 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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