发明名称 LOGIC VERIFYING METHOD
摘要 <p>PURPOSE:To provide the logic verifying method which enables output data to the multi-source signal line of a block where data are inputted and outputted to be observed or the input/output direction of data between the both to be decided. CONSTITUTION:The signal line 11 is multiple sources and has (m) sources 12 outside the block 10 and (n) sources 13 in the block 10. In the block 10, a signal line 14 and an output data observing circuit 15 are added, and the connection destination of the sources 13 is moved from 11 to 14, which are connected by the circuit 15. At the moment of the change of the sources 12 or 13, the signal line 14 holds the output data of the block 10 as a value, so this is observed by a signal data processing means 18.</p>
申请公布号 JPH0830667(A) 申请公布日期 1996.02.02
申请号 JP19940166553 申请日期 1994.07.19
申请人 HITACHI LTD 发明人 YAMAMOTO WATARU;ITO MASAKI;TAKAMINE YOSHIO
分类号 G06F17/50;G06F17/00;G06F19/00;G06Q50/00;G06Q50/04 主分类号 G06F17/50
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