发明名称 DIGITAL DATA CODER
摘要 PURPOSE:To attain a high processing speed for the coder compressing digital data. CONSTITUTION:Word length information Im(n) generated by a word length information generating circuit 12 is received by a correction information generating circuit 13 in the unit of blocks, in which what bit number of bit number indicated from the word length information Im(n) is further to be reduced is discriminated based on the integrated information for each block. The word length information Im(n) is corrected by a word length correction circuit 14 according to correction information Cm(n) according to the result of discrimination to generate proper word length information Wm(n). Audio data ADOUT in which the total bit number of one block is limited within an object number are obtained by coding data AM(n) at a coding circuit 15 based on the word length information Wm(n) without repetition of generation of the word length information Im(n) and coding processing of the data Am(n).
申请公布号 JPH0832453(A) 申请公布日期 1996.02.02
申请号 JP19940165476 申请日期 1994.07.18
申请人 SANYO ELECTRIC CO LTD 发明人 NAGAO FUMIAKI
分类号 G11B20/10;G10L19/00;G10L19/02;H03M7/30;H03M7/40;(IPC1-7):H03M7/30;G10L7/04;G10L9/18 主分类号 G11B20/10
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