| 摘要 |
A computer system and method are taught utilizing main memory and cache memory addressed in a novel manner to increase speed of operation of the computer system while minimizing the number of address pins required to fully address cache memory and main memory. A CPU address bus is shared between the cache memory and the main memory, having fewer bus leads than is required to fully address the entire content of main memory. When a memory access is desired, a first set of address bits are output by the CPU on the CPU address bus, which are a sufficient number of address bits to access cache memory. These bits also serve as the row bits for main memory, and are stored in a main memory address buffer. In the event of a cache hit, the appropriate data is read from or written to cache memory. Conversely, in the event of a cache miss, the row address bits stored in the main memory address buffer are strobed into main memory, and the CPU outputs the remaining memory bits, which serve as the column address bits required to access the desired memory location within the main memory. <MATH> |
