发明名称 |
Cache lock information feeding system using an address translator |
摘要 |
A method and apparatus for cache lock control are designed for use with a cache memory. The cache memory contains a number of data entries, each divided into segments for storing address information, data, and a cache lock bit, respectively. The cache lock bit, when set in a data entry, prevents updating the address and data in that data entry. An address translator is provided for converting virtual memory addresses to physical addresses. The address translator includes address entries which include at least one segment for storing cache lock information, and cache lock information is transferred from the address translator to the cache memory.
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申请公布号 |
US5487162(A) |
申请公布日期 |
1996.01.23 |
申请号 |
US19940338818 |
申请日期 |
1994.11.10 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. |
发明人 |
TANAKA, TETSUYA;TANIGUCHI, TAKASHI |
分类号 |
G06F12/12;(IPC1-7):G06F12/08 |
主分类号 |
G06F12/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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