| 摘要 |
PURPOSE:To attain the effective utilization of a memory at signal conversion and to reduce the signal delay. CONSTITUTION:Interface sections 20, 30 conducting input output control of a time slot signal and a time slot conversion section 40 conducting the sequence conversion of the time slot signal are connected in common to a bidirectional bus 10, the time slot signal is directly sent between the interface sections 20, 30 via the signal bus 10 when the time slot signal not requiring the sequence conversion is sent and when the sequence conversion is required, the time slot signal sent from the interface section is received by the time slot conversion section 40, in which the signal is subject to sequence conversion and the resulting signal is fed to the other interface section via the signal bus 10.
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