发明名称 LSI FOR DEFECT REMEDY AND MEMORY DEVICE
摘要 PURPOSE:To provide an LSI which can remedy a defect of a mounted DRAM and to provide a memory device which can remedy the defect of the DRAM generated after assembly. CONSTITUTION:The LSI for defect remedy consists of an interface part for the same address and control with DRAMs, an input/output interface corresponding to the memory device consisting of plural DRAMs, a nonvolatile storage circuit 3 which stores the chip addresses of the DRAMs and a defect address of an X system, a RAM part 4 for redundancy remedy consisting of an SRAM which has a word line selected with a comparison matching signal between an inputted X address and the defect address of the storage circuit and a column selected with a Y address signal, a selection part 6 which connects the data input/output bus of the RAM part for redundancy to a data input/output terminal, a data input/output part 7 which activates an input/output circuit corresponding to the selection, and a mask part 8 which outputs a signal for placing the output terminal of a DRAM judged to be defective in a high-impedance state.
申请公布号 JPH0816486(A) 申请公布日期 1996.01.19
申请号 JP19940170207 申请日期 1994.06.29
申请人 HITACHI LTD;HITACHI VLSI ENG CORP 发明人 WADA SHOJI;KEMIZAKI KANEHIDE;MURANAKA MASAYA;OGATA SHINKO;AOYANAGI HIDEAKI;KITAME TETSUYA;KATAYAMA MASAHIRO;KUBONO SHIYOUJI;SUZUKI YUKIE;MORINO MAKOTO;MIYATAKE SHINICHI;HARUFUJI SEIICHI;KOYAMA YOSHIHISA;ONO NOBUHIKO
分类号 G06F12/16;G11C29/00;G11C29/02;G11C29/44;H01L21/82;(IPC1-7):G06F12/16 主分类号 G06F12/16
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