发明名称 Amplifier circuit comprising an asymmetrical input and a symmetrical output.
摘要 The invention relates to a circuit arrangement having an unbalanced input via the input connections and a balanced voltage output via the output connections, whose input connection is connected to the input of a non-inverting amplifier with a gain of V, whose output is connected to the first addition input of a first addition stage whose output is connected to a first connection of a first winding of a balancing inductor, whose second connection forms the first output connection of the overall circuit and whose input connection is likewise connected to the input of an inverting amplifier having a gain -V, whose output is connected to the first addition input of a second addition stage whose output is connected to the first connection of a second winding of a balancing inductor, whose second connection forms the second output connection of the overall circuit, which is characterised in that a third winding is fitted on the inductor, the first connection of which third winding is connected to earth and the second connection of which third winding is connected to the current input of a current/voltage converter whose output is connected to the respectively second addition input of the addition stages.
申请公布号 EP0647020(A3) 申请公布日期 1996.01.17
申请号 EP19940113713 申请日期 1994.09.01
申请人 WERKSTAETTE FUER STUDIO-TECHNIK DIPL.-ING. HELLMUT HAUFE 发明人 BAUDISCH, WERNER
分类号 H03H11/32 主分类号 H03H11/32
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