发明名称
摘要 PURPOSE:To conduct a test in a short time by dividing cascaded counter units into >=2 with a signal outputted by a latch circuit group for preset data setting and putting them in operation. CONSTITUTION:When the cascaded counter units 11-1n are tested, specific data are set in latch circuit groups 21-2n which set preset data in the respective units and the output of a decoder 6 is validated. When the decoder 6 outputs the validated signal, a selector circuit 4 fixes the carry input terminal Ci of a counter unit 1m+1 at a H level. Consequently, counter unit groups of higher order than the counter unit 1m+1 and unit groups of lower order than the counter unit 1m operate as one counter respectively. For the purpose, the value of the output terminal 0 of each counter unit 1 is checked to test the operation of the counter in a short time.
申请公布号 JPH083514(B2) 申请公布日期 1996.01.17
申请号 JP19870251047 申请日期 1987.10.05
申请人 发明人
分类号 G01R31/317;G01R31/28;G01R31/3185;H03K21/00;H03K21/40;(IPC1-7):G01R31/28 主分类号 G01R31/317
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