| 摘要 |
The invention provides a BiCMOS logic gate circuitry comprising : input and output terminals ; an output driving section including two bipolar transistors (5, 6) in the form of totem pole connection between a high voltage line and a low voltage line in which an intermediate point between the two bipolar transistors (5, 6) is connected to the output terminal ; a base driving section including a plurality of MOS transistors and being connected to an input terminal for receiving an input signal and connected to bases of the bipolar transistors (5, 6) ; and a base cramping section including at least one cramping circuit (22) being connected to at least one of the bipolar transistors (5, 6) through its base for restricting a base potential of the at least one bipolar transistor (6) in the vicinity of the same potential as a base-emitter forward bias at which the bipolar transistor (6) turns ON so as to reduce the necessary time for charging a parasitic capacitance of the base of the at least one bipolar transistor (6). <IMAGE> |
